Just like any big city, electronics is evolving with great rapidity, such that both are running out of open space. The net result is a growth in the vertical direction. For a city, vertical growth promises more apartments, office space, and people per square mile. For electronics, there is the slowing of Moore’s law and the adoption of new advanced technology. That means chip developers cannot increase density and speed from shrinking processes and smaller transistors. Although they can increase the die capacity, this suffers from longer signal delays that reduce yield. That limits the expansion in X-Y directions, which means the only option remaining is building upwards.
Among the many established forms of vertical integration, there are 2.5D ICs, flip-chip technology, inter-die connectivity with wire bonding, and stacked packages. However, all these suffer from constraints that limit their value. Three-dimensional integrated circuits or 3-D ICs offer the highest density and speed.
Three-dimensional ICs are monolithic 3-D SoCs built on multiple active silicon layers. These layers use vertical interconnections between the different layers. So far, this is an emerging technology and has not been widely deployed. Furthermore, there are stacked 3-D ICs with multiple dies that manufacturers have stacked, aligned, and bonded into a single package. They use TSVs or through silicon vias, and a hybrid bonding technique to complete the inter-die communication. Stacked 3-D ICs are now commercially available, offering an option for larger dies or migration to leading-edge nodes that are very expensive.
Stacked 3-D ICs offer an ideal option for applications requiring more transistors in a given footprint. For instance, a mobile SoC requires high transistor densities but has limits on its footprint and height. Another example is cache memory chips. Manufacturers usually stack them on top of or below the processor to increase their bandwidth. This makes stacked 3-D ICs a natural choice for applications that are on the limits of a single die.
Vertical stacking offers a smaller footprint with faster interconnections compared to multiple packaged chips. Rather than a single large die, splitting it into several smaller dies provides a better yield. For the manufacturer, there is flexibility in stacking heterogeneous dies, as they can intermix various manufacturing processes and nodes. Moreover, it is possible to reuse existing chips without redesigning them or incorporating them into a single die. This offers a substantial reduction in risk and cost.
Although there are numerous benefits and opportunities from the use of stacked 3-D ICs, they also introduce new challenges. The architecture of 3-D silicone systems needs a more holistic approach, taking into account the third dimension. It is not sufficient to think of 3-D ICs only in terms of 2-D chips stacked on top of each other. Although it is necessary to optimize power, performance, and area in the familiar three-way approach, the optimization must be in every cubic millimeter rather than in every square millimeter. All tradeoff decisions must take into account the vertical dimension also. This requires making the tradeoffs across all design stages, including IP, architecture, chip packaging, implementation, and system analysis.
